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2012 2011 2010 2009 2008 2007
Master Theses 2012

Hui Xu

A Hierarchical Symbolic Simulator for Analog Circuit Design

He Zhang

A Symbolic Method for Time-Domain Analog Circuit Modeling

Xiaopeng Li

Hierarchical Symbolic Sensitivity Analysis with Application to Analog Design Optimization

Binbin Weng

Design Optimization of MOS Operational Amplifiers Using Finite Difference Sensitivity
Master Theses 2011

Weijian Huang

On Global Clock Mesh Syntheses And Optimization

Diming Ma

New Progress Of Symbolic Simulator Applications On Cmos Analog Circuit Design Automation
Master Theses 2010

An Chen

Symbolic Moment and Moment Sensitivity Computation Method With Application to Crosstalk Avoidance in Routing

Shuo Chen

A New Hierarchical Method for Symbolic Analog Circuit Simulation

Ji Li

Development Of A Graphical User Interface For An Analog Symbolic Simulator(grass) With Design Applications

Kunyuan Tan

An Investigation on the Dependence of Symbolic Simulator on Small Signal Models and the Application of Symbolic Simulator for Improving Analog Design Yield

Ting Wang

A Heuristic Algorithm to Improve the Performance of a Symbolic Analog Circuit Simulator

Mei Zeng

Symbolic Techniques For Band Width And Phase Margin Optimization In Analog Integrated Circuit Design
Master Theses 2009

Shijie Huang

A Survey On Multilevel Router Considering Crosstalk And Timing Optimization

An Liu

A Symbolic Approach To The Signal Integrity Of Multi-coupled Rlc Tree Circuits With Application

Xiaoxuan Meng

Symbolic AC Sensitivity Analysis for Analog Design

Di Xu

Symbolic Moment Calculation of RC Tree Circuit and its Application of Delay Metrics

Xuhong Yu

Statistical Interconnect Timing Analysis Based On Symbolic Method

Xiangyu Zhu

A Research On Low Cost Implementing Of Runtime Fault Diagnosis In Digital Integrated Circuits
Master Theses 2008

Zhigang Hao

Research On The High-speed Parametric Multi-port Interconnect Analysis Techniques

Liguo Jiang

Simultaneous Switch Noise Simulation Based on Macro-model

Xiaonan Li

A Survey On Timing Balance Based On Multilevel Routing Framework

Xiuyu Peng

RLC Parasitic Parameter Extraction and Reduced-Order Modeling of High-Frequency Transmission Lines

Liu Wang

Ibis Modeling And Simulation Method For Signal Integrity

Master Theses 2007

Weiwei Chen

A Symbolic Analog Circuit Simulator

Liqun Deng

Signal Integrity Analysis Base on Model Order Reduction

Jie Hong

Model Compiler and the Application in Interconnect Modeling, Signal Integrity