刘勇

刘勇 / 教授


电子邮箱:yongliu@sjtu.edu.cn
办公电话:34204546-1078
办公地点:微电子楼424室

 

 

哈佛大学, 美国麻萨诸塞州

    博士, 工程与应用科学学院, 2007年11月

     ♦  论文: CMOS Magnetic Cell Manipulator and CMOS NMR Biomolecular Sensor

    硕士, 工程与应用科学学院, 2006年

 

清华大学, 中国北京

    工学硕士, 微电子学与固体电子学, 微电子学研究所,2003年

     ♦  论文: SRAM IP核与低功耗电路研究

     ♦  GPA: 1/30

    工学学士, 微电子学, 电子工程系, 2000年

     ♦  清华大学优秀毕业论文奖

 

刘勇,中组部“青年千人”计划获得者,上海千人计划获得者,上海交通大学教授。分别于2000年、2003年获清华大学本科、硕士学位,2007年美国哈佛大学博士毕业,在美国IBM沃森研究中心(IBM T.J. Watson Research)工作8年,主要从事高速芯片互连的研究。2015年6月加入上海交通大学。

 

刘勇教授主要研究领域为高速数据通信集成电路以及生物医疗芯片。已发表学术论文30多篇,在集成电路行业最顶级国际会议IEEE International Solid- State Circuits Conference (ISSCC) 上发表论文7篇,第一作者5篇。在集成电路行业最顶级期刊IEEE Journal of Solid-State Circuits(JSSC)上发表论文6篇。多次获论文大奖,包括2009年ISSCC会议的Beatrice Winner Award奖和2009年JSSC期刊最佳论文奖。著有学术专著章节2章,已获得美国专利9项。

本课题组招聘教师及研究人员,详见人才招聘公告

 

获奖情况:

    ♦  集成电路最顶级期刊固态电路期刊IEEE Journal of Solid-State Circuits (JSSC) 最佳论文奖 (Best Paper Award), 2009.  (JSSC: the most prestigious journal in integrated circuits design field)

    ♦  集成电路最顶级国际会议国际固态电路会议 (IEEE Solid-State Circuits Conference, 简称ISSCC, 被誉为集成电路的奥林匹克) Beatrice Winner Award for Editorial Excellence,  2009.

    ♦  受邀在2013年ISSCC的论坛(Forum: Emerging Technologies for Wireline Communication)上做技术报告:High-Speed and Low-Power 2.5D and 3D I/O Technologies

    ♦  3IBM研究部门奖 (IBM Research Division Awards):2012年.

    ♦  3IBM发明成果奖 (IBM Invention Achievement Award):2011年,2012年,2014年.

    ♦  IBM首个专利奖 (IBM First Patent Award), 2008年.

    ♦  最佳张贴奖 (Best Poster Award), 南台湾微纳研究研讨会 (South Taiwan Micro Nano Research Workshop), 2006年.

    ♦  优秀学生设计奖, 美国Analog Devices公司, 2004年.

    ♦  研究生奖学金, 哈佛大学, 2003年.

    ♦  第四届全国研究生电子设计自动化竞赛个人二等奖 (第4名), 中国, 2002年.

    ♦  摩托罗拉奖学金, 清华大学, 2001年.

    ♦  优秀毕业论文奖, 清华大学, 2000年.

    ♦  优秀学生奖学金, 清华大学, 1997-1999年.

    ♦  北京本科物理竞赛三等奖, 1997年.

    ♦  Seagate 奖学金, 清华大学, 1996年.

    ♦  中国高中数学奥林匹克竞赛全国三等奖 (河北省第三名), 1996年.

    ♦  多项高中数学物理和英语竞赛获奖, 中国, 1995-96年.

 

学术活动:

    ♦  受邀在2013年ISSCC的论坛(Forum: Emerging Technologies for Wireline Communication)上做技术报告:High-Speed and Low-Power 2.5D and 3D I/O Technologies

    ♦  担任了2012年Asian Solid-State Circuits Conference (A-SSCC) 的Technical Program Committee的委员.

    ♦  受邀担任VLSI Design杂志的Lead Guest Editor。

    ♦  担任SRC在研究项目的IBM方面的技术联络人。

    ♦  受邀为以下国际学术会议和杂志审稿:

  1. IEEE Journal of Solid-State Circuits (JSSC)
  2. IEEE International Solid-State Circuits Conference (ISSCC)
  3. IEEE VLSI Symposium (VLSI)
  4. IEEE Custom Integrated Circuits Conference (CICC)
  5. IEEE Asian Solid-State Circuits Conference (A-SSCC)
  6. IEEE Transactions on Circuits and Systems
  7. IEEE Transactions on Biomedical Circuits and Systems
  8. International Symposium on Circuits and Systems (ISCAS)
  9. Electronics letters
  10. Journal of Electrical and Computer Engineering
  11. IEEE International 3D System Integration Conference (3DIC)
  12. International Symposium on VLSI Design, Automation & Test
  13. Solid State Electronics

 

发表论文:

高速数据通信电路 (High-Speed I/O)

[1]     T. Dickson, Yong Liu, S. Rylov, A. Agrawal, S. Kim, P. Hsieh, J. Bulzacchelli, M. Ferriss, H. Ainspan, A. Rylyakov, B. Parker, C. Baks, L. Shan, Y. Kwark, J. Tierno, and D. Friedman, “A 1.4-pJ/b, Power-Scalable 16×12-Gb/s Source-Synchronous I/O with DFE Receiver in 32nm SOI CMOS Technology,” IEEE Journal of Solid-State Circuits (JSSC), to be expected, 2015.

[2]     T. Dickson, Yong Liu, S. Rylov, A. Agrawal, S. Kim, P. Hsieh, J. Bulzacchelli, M. Ferriss, H. Ainspan, A. Rylyakov, B. Parker, C. Baks, L. Shan, Y. Kwark, J. Tierno, and D. Friedman, “A 1.4-pJ/b, Power-Scalable 16×12-Gb/s Source-Synchronous I/O with DFE Receiver in 32nm SOI CMOS Technology,” IEEE Custom Integrated Circuits Conference (CICC),  Sept. 2014.

[3]        Y. Liu, P. Hsieh, S. Kim, J. Seo, R. Montoye, L. Chang, J. Tierno, and D. Friedman, “A 0.1pJ/b 5-to-10Gb/s Charge-Recycling Stacked Low-Power I/O for On-Chip Signaling in 45nm CMOS SOI,” IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, pp. 400-401, Feb. 2013.

[4]        M. Sanduleanu, A. Valdes-Garcia, Y. Liu, B. Parker, S. Shlafman, B. Sheinman, D. Elad,
S.  Reynolds and D. Friedman, “A 60GHz, Linear, Direct Down-Conversion Mixer with mm-Wave Tunability in 32nm CMOS SOI,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2013.

[5]        A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno, and D. Friedman, “A 19Gb/s Serial Link Receiver with Both 4-tap FFE and 5-tap DFE Functions in 45nm SOI CMOS,” (Special issue paper) IEEE Journal of Solid-State Circuits (JSSC), pp. 3220-3231, Dec. 2012.

[6]        X. Gu, J. Silberman, Y. Liu and X. Duan, “Mitigating TSV-induced Substrate Noise Coupling in 3-D IC Using Buried Interface Contacts,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 75-78, 2012.

[7]        J. Knickerbocker, P. Andry, E. Colgan, B. Dang, T. Dickson, X. Gu, C. Haymes, C. Jahnes, Y. Liu, J. Maria, R. Polastre, C. Tsang, L. Turlapati, B. Webb, L. Wiggins and S. Wright, “2.5D and 3D Technology Challenges and Test Vehicle Demonstrations,” IEEE Electronic Components and Technology Conference (ECTC), pp. 1068-1076, 2012.

[8]      T. Dickson, Y. Liu, S. Rylov, B. Dang, C. Tsang, P. Andry, J. Bulzacchelli, H. Ainspan, X. Gu,               L. Turlapati, M. Beakes, B. Parker, J. Knickerbocker, and D. Friedman, “An 8×10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects,” (Special issue paper) IEEE Journal of Solid-State Circuits (JSSC), vo. 47, no. 4, pp. 884-896, April 2012.

[9]      Y. Liu, W. Luk, and D. Friedman, “A Compact Low-Power 3D I/O in 45nm CMOS,” ISSCC Dig. of Tech. Papers, pp. 142-143, Feb. 2012.

[10]      A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno, and D. Friedman, “A 19Gb/s Serial Link Receiver with Both 4-Tap FFE and 5-Tap DFE Functions in 45nm SOI CMOS,” ISSCC Dig. of Tech. Papers, pp. 134-135, Feb. 2012.

[11]      Y. Liu, B. Kim, T. Dickson, J. Bulzacchelli, and D. Friedman, “A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” IEEE Solid-State Circuits, Newsletter, Vol. 16, Issue 1, 2011.

[12]    T. Dickson, Y. Liu, S. Rylov, B. Dang, C. Tsang, P. Andry, J. Bulzacchelli, H. Ainspan, X. Gu,               L. Turlapati, M. Beakes, B. Parker, J. Knickerbocker, and D. Friedman, “An 8×10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects,” Proceedings of IEEE VLSI Symposium, pp. 80-81, June 2011.

[13]    J Maria, B Dang, SL Wright, CK Tsang, P Andry, R Polastre, Yong Liu, L Wiggins, and JU Knickerbocker, “3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections,” IEEE Electronic Components and Technology Conference (ECTC), pp. 268-273, 2011.

[14]      F. Liu, X. Gu, K. A. Jenkins, E. Cartier, Y. Liu, P. Song, and S. J. Koester, “Through-Silicon Via Inductance and Capacitance Characterization,” 60th Electronic Components and Technology Conference (ECTC), June, 2010.

[15]    Y. Liu, B. Kim, T. Dickson, J. Bulzacchelli, and D. Friedman, “A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” ISSCC Dig. of Tech. Papers, pp. 182-183, Feb. 2009.   (Beatrice Winner Award for Editorial Excellence, ISSCC, 2009)

[16]    B. Kim, Y. Liu, T. Dickson, J. Bulzacchelli, and D. Friedman, “A 10Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65nm CMOS,” (Special issue paper) IEEE Journal of Solid-State Circuits (JSSC), vo. 44, no. 12, pp. 3526-3538, Dec. 2009. (JSSC Best Paper Award, 2009)

类脑芯片 (Cognitive Chip)

[17]    B.  Rajendran,  Y. Liu, J. Seo, K. Gopalakrishan, D. Friedman, and M. Ritter, “RRAM Devices for Large Neuromorphic Systems,” Non-Volatile Memories Workshop,  UCSD, March, 2013.

[18]   B.  Rajendran,  Y. Liu, J. Seo, K. Gopalakrishan, D. Friedman, and M. Ritter, “Specifications of Nanoscale Devices and Circuitsfor Neuromorphic Computational Systems,” IEEE Transactions on Electron Devices, pp. 246-253, Jan. 2013.

[19]    J. Seo, B. Brezzo, Y. Liu, B. Parker, S. Esser, R. Montoye, B. Rajendran, J. Tierno, L. Chang, D. Modha, and D. Friedman, “A 45nm CMOS Neuromorphic Chip with a Scalable Architecture for Learning in Networks of Spiking Neurons,” IEEE Custom Integrated Circuits Conference (CICC),  Sept. 2011.

高速时钟电路

[20]     K. Woo, Y. Liu, E. Nam, and D. Ham, “Fast-lock Hybrid PLL Combining Fractional-N & Integer-N Modes of Differing Bandwidths,” IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 2, pp. 379-389, Feb. 2008.

[21]    K. Woo, Y. Liu, and D. Ham, “Fast-lock Hybrid PLL Combining Fractional- & Integer-N Modes of Differing Bandwidths,” Proceedings of IEEE VLSI Symposium, pp. 260-261, June 2007.

[22]    Y. Liu, W. Rhee, D. Friedman, and D. Ham, “All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs,” ISSCC Dig. of Tech. Papers, pp.176-177, Feb. 2007.

生物芯片(Integrated Circuits for Biology)

[23]   N. Sun, Y. Liu, L. Qin, H. Lee, R. M. Westervelt, and D. Ham, “Small NMR Biomolecular Sensors,” (Invited paper) Journal of Solid-State Electronics, pp. 13-21, June 2013.

[24]   N. Sun, Y. Liu, H. Lee, R. M. Westervelt, and D. Ham, “Silicon RF NMR biomolecular sensor – Review,” (Invited paper) Proceedings of European Solid-State Device Research Conference (ESSDERC), pp. 14-17, Sept. 2012.

[25]   N. Sun, Y. Liu, H. Lee, R. M. Westervelt, and D. Ham, “Silicon RF NMR biomolecular sensor – Review,” (Invited paper) Proceedings of International Symposium on VLSI Design, Automation & Test (VLSI-DAT), pp.121-124, Apr. 2010.

[26]      N. Sun, Y. Liu, H. Lee, R. Weissleder, and D. Ham, “CMOS RF Biosensor Utilizing Nuclear Magnetic Resonance,” IEEE Journal of Solid-State Circuits  (JSSC), vol. 44, no. 5, pp.1629-1643, May 2009.

[27]      Y. Liu, S. Nan, H. Lee, R. Weissleder, and D. Ham, “CMOS Mini Nuclear Magnetic Resonance System and its Application for Biomolecular Sensing,” ISSCC Dig. of Tech. Papers, pp.140-141, Feb. 2008.

[28]     H. Lee, Y. Liu, D. Ham, and R. M. Westervelt, “Integrated cell manipulation system- CMOS/microfluidic hybrid,” Lab on a Chip, vol. 7, no. 3, pp. 331-337, March 2007.

[29]    Y. Liu, H. Lee, R. M. Westervelt, and D. Ham, “CMOS Meets Bio,” (Invited paper) Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 419-422, Nov. 2006.

[30]    H Lee, Y. Liu, R. M. Westervelt, and D. Ham, “IC/Microfluidic Hybrid System for Magnetic Manipulation of Biological Cells,” IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 6, pp.1471-1480, June 2006.

[31]    Y. Liu, H. Lee, R. M. Westervelt, and D. Ham, “IC/Microfluidic Hybrid System for Biology Applications: Review,” (Invited paper) Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 174-179, Oct. 2005.

[32]    H. Lee, Y. Liu, E. Alsberg, D. E. Ingber, R. M. Westervelt, and D. Ham, “An IC/Microfluidic Hybrid Microsystem for 2D Magnetic Manipulation of Individual Biological Cells,” ISSCC Dig. of Tech. Papers, pp. 80-81, Feb. 2005.

SRAM

[33]    Y. Liu and Z. Gao, “Timing Analysis of Transistor Stack for Leakage Power Saving,” Proceedings of IEEE International Conference on Electronics, Circuits and Systems, pp. 41-44, Sept. 2002.

[34]    Y. Liu, Z. Gao and X. He, “A Flexible Embedded SRAM Compiler,” Proceedings of IEEE International Workshop on Electronic Design, Test & Applications, pp. 474-476, Jan. 2002.

[35]      Y. Liu, Z. Gao, “A Flexible SRAM Compiler for Embedded Application,” Proceedings of IEEE International Conference on Solid-State and Integrated-Circuit Technology, pp. 213-216, Oct. 2001. 

专著章节

[36]     N. Sun, Y. Liu, and Donhee Ham, “Chapter 16: Low cost diagnostics − RF designer’s approach,” invited book chapter in CMOS Biomicrosystems: Where Electronics Meet Biology, (edited by K. Iniewski), John Wiley & Sons, Inc., 2011.

[37]    Y. Liu, “Chapter 5: CMOS Magnetophoresis” in the book CMOS bio-technology, (edited by H. Lee, D. Ham, and R. M. Westervelt), pp. 103-144, Springer, 2007.

 

 

专利 (已颁发: 9, 申请中: 10)

[1]        Patent 8,809,995: “Through silicon via noise suppression using buried interface contacts,” with X. Duan, X. Gu, and J. Silberman, IBM, Aug. 2014.

[2]        Patent 8,797,084: “Calibration schemes for charge-recycling stacked voltage domains,” with D. Friedman and J. Tierno, IBM, Aug. 2014.

[3]        Patent 8,774,228: “Timing recovery method and apparatus for an input/output bus with link redundancy,” with J. Bulzacchelli, T. Dickson, D. Friedman and S. Rylov, IBM, July 2014.

[4]        Patent 8,410,816: “Low-swing signaling scheme for data communication,” with W. Luk and D. Friedman, IBM, April 2013.

[5]      Patent 8,331,164: “Compact low-power asynchronous resistor-based memory read operation and circuit,” with S. Kim and B. Rajendran, IBM, Dec. 2012.

[6]        Patent 7,511,543: “Automatic static phase error and jitter compensation in PLL circuits,” with W. Rhee and D. Friedman, IBM, Mar. 2009.

[7]        Patent 7,274,262: “Method and apparatus based on coplanar striplines,” with D. Ham and W. Andress, Harvard, Sept. 2007.

[8]      Patent 7,242,272: “Method and apparatus based on coplanar striplines,” with D. Ham and W. Andress, Harvard, July 2007.

[9]      Patent 7,091,802: “Method and apparatus based on coplanar striplines,” with D. Ham and W. Andress, Harvard, Aug. 2006.