Seminar: Why Design for Test (DFT) and Where It Goes

Seminar Information


Title: Why Design for Test (DFT) and Where It Goes

Time: 10:00-11:30am,March 28, 2013(Thursday)

Location: Room 401, School of Microelectronics

Speaker: Dr. Liyang Lai (Mentor Graphics)

Host: Dr. Xiaoyong Li



With increasing complexity and size of integrated circuits, today’s large SoCs are more and more difficult to test and verify. It is not only very expensive but also extremely time consuming. This challenge is going to stay with Moore’s law continuing to take effect. IC companies are putting more and more resources to tackle these problems. The goal is to ensure fast time-to-market, high product quality,low test cost, and quick yield ramp-up.

In order to achieve this goal, at the early stage of architectural design testing has to be taken into account. The effect of DFT goes through the entire design flow but it does not stop there. This presentation will review some of important roles that DFT plays in post-silicon verification/debug, manufacture test and yield analysis. Hopefully this talk can serve as a starting point for discussion that we could learn and benefit from each other.